Linear programming based design of reconfigurable network on chip on eFPGA

Multiprocessors system on chip are expected to be used for multiple applications which might exhibit distinct communication patterns. Finding a common efficient network on chip for these multiple applications might be simply impossible due to the diverging requirements. Reconfigurable network on chip is a potential solution in which the network is reconfigured before application execution in order to match the application specific requirements. Implementation of this reconfigurability might be done using eFPGA. In this paper we propose a methodology to specify the area dimension of reconfigurable eFPGA for NoC (Network on Chip). Various objective functions are used to drive out study. Experimental results show the effectiveness of our approach.