Design and application of reusable SoC verification platform

This paper puts forward a kind of reusable SoC verification platform which reduces the complexity of SoC verification. The verification platform supports a mixed functional verification which includes both the IP core level and system level. All test program and functional module can completely be reused in different verification phase, which avoids the reconstruction of the platform and keeps the consistency of the platform from the simulation environment to the FPGA verification environment. The experimental results show that, the reusability of the verification platform constructed in this method reaches more than 70%, and the verification efficiency is improved by 45%.