DocumentCode
3384422
Title
A wide-range DLL-based clock generator with phase error calibration
Author
Cheng, Kuo-Hsing ; Su, Chia-Wei ; Wu, Meng-Jhe ; Chang, Yu-Ling
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Jhongli
fYear
2008
fDate
Aug. 31 2008-Sept. 3 2008
Firstpage
798
Lastpage
801
Abstract
In this paper, a wide-range operation and phase error calibration DLL-based clock generator is proposed. By using multi-band voltage controlled delay line (MBVCDL) and frequency multiplier to expand the operation frequency range of clock generator. The proposed clock generator uses detect window phase detector (DWPD) to effectively reduce phase error. The proposed DLL can reduce the maximum phase error form 3.57deg to 1.098deg of DLL multiphase output at 250 MHz. The simulation results show that the proposed DLL operates from 25 MHz to 250 MHz and the frequency multiplier synthesizes frequency from 250 MHz to 2.5 GHz. The power dissipation and the peak-to-peak jitter are 10.1 mW and 22.6 ps at 2.5 GHz frequency multiplier output frequency.
Keywords
clock and data recovery circuits; digital phase locked loops; frequency multipliers; jitter; detect window phase detector; frequency 25 MHz to 250 MHz; frequency 250 MHz to 2.5 GHz; frequency multiplier; multiband voltage controlled delay line; peak-to-peak jitter; phase error calibration; power dissipation; wide-range DLL-based clock generator; Calibration; Charge pumps; Circuits; Clocks; Delay lines; Frequency synthesizers; Jitter; Phase detection; Phase frequency detector; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location
St. Julien´s
Print_ISBN
978-1-4244-2181-7
Electronic_ISBN
978-1-4244-2182-4
Type
conf
DOI
10.1109/ICECS.2008.4674974
Filename
4674974
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