A novel high-accuracy clock stabilizer with 50% duty cycle

This paper presents a novel synchronous 50% clock duty cycle stabilizer (CDCS). The proposed circuit consists of a leading edge pulse generator, clock generator, charge pump loop and a pulse width extender. Leading edge pulse generator employs the edge of input clock as a starting pulse of the output clock to realize the synchronization. By utilizing the charge pump loop to control the discharging current in pulse width extender circuit, the output clock duty cycle converges to 50% when CDCS reaches its stable state. The chip is designed and fabricated in TSMC 0.18μm 1P6M CMOS process. The core area is about 0.2×0.2mm. The circuit can stabilize an input clock with 10 to 125MHz frequency and 10%~90% duty cycle.