Title :
Variation-tolerant design of D-flipflops
Author :
Sunagawa, Hiroki ; Onodera, Hidetoshi
Author_Institution :
Dept. Commun. & Comput. Eng., Kyoto Univ., Kyoto, Japan
Abstract :
This paper discusses vulnerability of a D-flipflop (D-FF) under within-die (WID) variation. The effect of WID variability on D-FF timing characteristics is examined and it is revealed that the setup time of a D-FF becomes larger than that of the worst corner condition. In order to suppress this “worse-than-the-worst-corner” behavior, variation-tolerant D-FFs are proposed and verified in a 65nm process, including a D-FF with over-sized clock drivers which reduces performance variability by 29% at 1.2V and 55% at 0.7V with power overhead of 14%.
Keywords :
clocks; driver circuits; flip-flops; logic design; D-flip-flops timing characteristics; over-sized clock driver; size 65 nm; variation-tolerant design; voltage 0.7 V; voltage 1.2 V; within-die variation;
Conference_Titel :
SOC Conference (SOCC), 2010 IEEE International
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-6682-5
DOI :
10.1109/SOCC.2010.5784732
