Design and performance considerations for an on-chip jitter analysis system

In this paper we present an accurate jitter analysis method for use with built-in jitter measurement systems in serial high-speed communications. The method is based on the analysis of jitter distributions, and thus suffers from hardware design aspects, such as the amount of collected jitter samples or the timing resolution. Design equations and empirical relations are derived to characterize these key parameters, in order to provide an optimized system performance. This allows the method to be utilized on-chip for production testing or as a design for test structure.