DocumentCode :
3384549
Title :
Rule-based equivalence checking of system-level design descriptions
Author :
Yoshida, Hiroaki ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan
fYear :
2009
fDate :
23-25 July 2009
Firstpage :
1139
Lastpage :
1143
Abstract :
This paper presents our study on rule-based equivalence checking of system-level design descriptions. The rule-based equivalence checking proves the equivalence of two system-level design descriptions by applying equivalence rules in a bottom-up manner. In this paper, we first introduce our intermediate representation of system-level design, and then show a set of representative equivalence rules. Since our equivalence checking method is based on potential internal equivalences identified by using random simulation, we also present how to prove the equivalence based on such potential internal equivalences. Finally, we explain our implementation of the rule-based equivalence checker and demonstrate its feasibility and efficiency using an example design.
Keywords :
VLSI; circuit CAD; integrated circuit design; equivalence checking method; potential internal equivalences; representative equivalence rules; rule-based equivalence checking; system-level design descriptions; Costs; Design automation; Formal verification; Hardware; Large-scale systems; Lead compounds; Productivity; Software design; System-level design; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on
Conference_Location :
Milpitas, CA
Print_ISBN :
978-1-4244-4886-9
Electronic_ISBN :
978-1-4244-4888-3
Type :
conf
DOI :
10.1109/ICCCAS.2009.5250314
Filename :
5250314
Link To Document :
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