A low-latency NoC router with lookahead bypass

Packet-switched networks on chip are emerging communication fabric to resolve the scalability and bandwidth limitation inherent in shared buses and dedicated links. However current state-of-the-art on-chip network routers suffer from latency overhead. In this work, we propose a new router which makes use of dynamic lookahead bypass to reduce latency. Special lookahead controlling pipeline is applied to speed up allocation computations so that the input buffers´ bypassing rate increases. Lookahead pipeline and bypasses not only can reduce network latency but can save the energy due to writing and reading buffers. Analysis and simulation results using different traffic patterns prove that the architecture can significantly improve packet latency by up to 32.1% over a state-of-art router design and costs only a small silicon area overhead.