Title :
A 4GS/s 3b two-way time-interleaved ADC in 0.13um CMOS
Author :
Gu, Chunchen ; Zhao, Yi ; Hong, Zhiliang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
A time-interleaved ADC,2 channels each consisting of a track-and-hold circuit with self-biased buffer and a 2GS/s flash ADC,is presented. The sub-ADC is composed of one-stage pre-amplifiers, latches and standard digital encoders with TSPC D-flip-flops. A half-reset latch is proposed to operate at sampling rate of 2GS/s with improved power consumption. 2.91b ENOB and 25.46dB SFDR are gotten by simulation at Nyquist frequency. The FoM of the ADC including T/H is 1.51 pJ/conv.-step.
Keywords :
CMOS integrated circuits; Nyquist criterion; analogue-digital conversion; buffer circuits; flip-flops; preamplifiers; sample and hold circuits; CMOS integrated circuit; Nyquist frequency; TSPC D-flip-flops; flash ADC; half-reset latch; latches; one-stage pre-amplifiers; self-biased buffer; size 0.13 mum; standard digital encoders; sub-ADC; track-and-hold circuit; two-way time-interleaved ADC; Calibration; Laboratories; Lead; Logic gates; Switches; Time frequency analysis; Wireless communication;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157376
