Title :
Ultra low voltage and, nor and XOR CMOS gates
Author :
Berg, Y. ; Mirmotahari, O. ; Aunet, S.
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo
fDate :
Aug. 31 2008-Sept. 3 2008
Abstract :
In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.
Keywords :
CMOS logic circuits; logic gates; NAND gates; NOR CMOS gate; XOR CMOS gate; complementary CMOS gates; delay margin; electrical characteristics; noise margin; size 90 nm; threshold holdgates; ultralow-voltage CMOS logic style; CMOS logic circuits; CMOS process; CMOS technology; Delay; Energy consumption; Informatics; Logic gates; Low voltage; Pulse inverters; Variable structure systems;
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
DOI :
10.1109/ICECS.2008.4674986
