TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures

An efficient and accurate performance analysis technique is indispensable for developing on-chip communication architectures. However, traditional approaches cannot achieve both efficiency and accuracy. To address this problem, we present a FPGA-based trace-driven emulation framework named TERA. TERA uses FPGA to accelerate both trace extraction and trace execution. To avoid the potential influence of inaccurate models on trace extraction, TERA captures traces based on the hardware platform for the target SoC. In addition, TERA uses classified traffic generators as well as a cycle-accurate memory controller model to improve the accuracy of trace execution. Experimental results demonstrate that TERA is over three orders of magnitude faster than cycle-accurate software simulation, and the variation of TERA from the real chip is less than 4.15%.