DocumentCode
3384934
Title
Development of cost effective sampling strategy for in-line monitoring
Author
Tomlinson, Wanda ; Nurani, Raman K. ; Burns, Mark ; Shanthikumar, J. George
Author_Institution
IBM Corp., Burlington, VT, USA
fYear
1997
fDate
10-12 Sep 1997
Firstpage
8
Lastpage
12
Abstract
This paper presents the details of a study undertaken at the IBM wafer fabrication facility to determine the optimal in-line inspection sampling plan for poly process module. During the study several lots at multiple processing points were inspected. The data was collected and analyzed to characterize the process baseline and excursions. This was then used to determine the cost of current sampling plan and what the best sampling plan would be to both minimize risk to the product and minimize cost of doing inspections. The optimal sample plan was then modified to also minimize the cycle time through the inspection process. We also present the results of a new SPC model which explicitly accounts for the lot-to-lot and wafer-to wafer variations. We illustrate that the application of traditional policies could increase the “lots-at-risk” by as much as 17%
Keywords
inspection; integrated circuit manufacture; monitoring; statistical process control; IBM wafer fabrication facility; SPC model; cost effective sampling strategy; cycle time; in-line monitoring; inspection sampling plan; lot-to-lot variations; multiple processing points; poly process module; process baseline; wafer-to wafer variations; Cost function; Fabrication; Image sampling; Inspection; Investments; Monitoring; Process control; Sampling methods; Semiconductor device modeling; Uncertainty;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
Conference_Location
Cambridge, MA
ISSN
1078-8743
Print_ISBN
0-7803-4050-7
Type
conf
DOI
10.1109/ASMC.1997.630696
Filename
630696
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