Implementation of an MHT-based object detection algorithm on a 2-D processor mesh

The mapping of multistage hypothesis testing (MHT)-based algorithms to two-dimensional mesh architectures is discussed. How the interprocessor communication overhead varies as a function of the grain-size of the architecture is discussed. The speedup achievable by a processor mesh relative to a single processor is calculated as a function of the cost of interprocessor communication. It is shown that the smaller the mesh grain-size, the greater the speedup of the MHT-based algorithm, even for very expensive interprocessor communication costs