A flexible LDPC decoder architecture supporting two decoding algorithms

Author

Huang, Shuangqu ; Bao, Dan ; Xiang, Bo ; Chen, Yun ; Zeng, Xiaoyang

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3929

Lastpage

3932

Abstract

In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS process with a total area of 6.3 mm2 and maximum clock frequency of 260 MHz. The estimated comsumption is 270 mW when operates at 125 MHz and 1.2V supply.

Keywords

CMOS integrated circuits; block codes; clocks; decoding; parity check codes; CMOS process; IEEE 802.16e; TDMP; TPMP; area-efficient decoder architecture; block-LDPC codes; clock frequency; flexible LDPC decoder architecture; frequency 260 MHz; low-density parity-check code; programmable decoder architecture; size 0.13 mum; Application specific integrated circuits; CMOS process; Clocks; Frequency; Iterative algorithms; Iterative decoding; Laboratories; Message passing; Parity check codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537686

Filename

5537686