Title :
High-Performance random data lookup for network processing
Author :
Yang, Xin ; Sezer, Sakir ; McCanny, John ; Burns, Dwayne
Author_Institution :
ECIT Inst., Queen´´s Univ. Belfast, Belfast, UK
Abstract :
Because the speed degradation and on-chip resources limit large CAM applications on SoCs and FPGAs, Hash-CAM architectures are attractive concepts combining the space efficiency of hashing algorithm and fast lookup character of the CAM for collision resolutions. In proposed Hash-CAM circuit, single and double hashing schemes are explored and compared. It proves that, with parallel CRC circuit and pipeline approach, dual hashing (or multiple hashing) scheme with multiple smaller memory blocks for the hash table is an efficient way to implement Hash-CAM architectures, for medium size lookup table of thousands of entries.
Keywords :
cryptography; field programmable gate arrays; system-on-chip; FPGA; Hash-CAM architectures; SoC; collision resolutions; dual hashing; hashing algorithm; high-performance random data lookup; multiple hashing; multiple smaller memory blocks; network processing; on-chip resources; parallel CRC circuit; pipeline approach; Computer aided manufacturing; Computer architecture; Field programmable gate arrays; Hardware; Polynomials; Random access memory; System-on-a-chip;
Conference_Titel :
SOC Conference (SOCC), 2010 IEEE International
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-6682-5
DOI :
10.1109/SOCC.2010.5784758
