Power optimization through edge reduction in LUT-based FPGA technology mapping

This paper considers the problem of lookup table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm, PowerMap_er. This paper describes a technique that reduces power consumption by reducing the edge count in mapped network. The purpose of this technique is to reduce edge and power by considering routability in early steps of the CAD flow. Since routability can be improved by reducing edge count in mapping, power would be optimized after placement and routing. The main idea of our algorithm is to exploit the ldquocut enumerationrdquo technique. Moreover, iterations of area and edge recoveries are deployed, and more effective edge cost function is proposed. The experimental results indicate that our algorithm reduces the average power consumption by up to 18.1%, the edge number by up to 10%, and the average number of LUTs by up to 6.8 % over an existing MacroMap algorithm. And compared to PowerMinMap-d ^[15], we achieved 12.74% power savings and 15.66% area reduction.