Joint equalization technique and special spacing rules for link design

Achieving high link speed and reliability is a key challenge in network-on-chip (NoC) design. To address the challenge,, we propose the equalization scheme and the joint equalization technique and special spacing rules solution for improving the communication speed and reliability for NoC links in the paper. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the links. The experiment results for a 10-mm 32-bit link in 0.13um CMOS process technology show that 1.28times speedup is achievable by equalization alone with 1% area overhead. The simulation results show that the joint equalization and increasing spacing of the uncoded link can reduce 50% delay and save 42% power only with 50% area overhead compared with the minimum-spaced uncoded links. The BER of the links is improved from 10^-5 to 10^-24.