Title :
A scalable offset-cancelled current/voltage sense amplifier
Author :
Attarzadeh, Hourieh ; Sharifkhani, Mohammad ; Jahinuzzaman, Shah M.
Author_Institution :
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
fDate :
May 30 2010-June 2 2010
Abstract :
The application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. The offset cancellation phase takes place in parallel to the wordline decoding time in order to speed up the current sensing. The proposed scheme requires a small power budget due to a self shut off mechanism. In addition to presenting a comparison with the conventional schemes, the efficiency of the proposed scheme is evaluated in 90nm, 130nm and 180nm CMOS technologies to show the scalability and the robustness of the proposed scheme under smaller voltage headroom.
Keywords :
CMOS analogue integrated circuits; SRAM chips; amplifiers; capacitance; CMOS technology; DC offset; bitline capacitance; cell access time; cell current; current sense amplifier; current sensing; device mismatch; offset cancellation; power budget; scaled SRAM design; size 130 nm; size 180 nm; size 90 nm; voltage headroom; voltage sense amplifier; wordline decoding time; CMOS technology; Capacitance; Circuits; Decoding; Energy consumption; Random access memory; Resource description framework; Robustness; Scalability; Threshold voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537701
