A PVT Tolerant sub-mA PLL in 65nm CMOS process

A sub-mA phase-locked loop fabricated in 65 nm digital CMOS process is presented. The impact of process variation is removed by an open-loop calibration that is performed only during the PLL start-up, which is opened during normal operation. The dual-loop PLL architecture is adopted to achieve process independent damping factor and pole-zero separation. A new phase frequency detector embedded with level shifter is introduced. Careful power supply partitioning is explored to minimize the noise coupling. The proposed PLL achieves 3.1 ps rms jitter running at 1.6 GHz consuming only 0.94 mA.