High speed CDR using a novel binary phase detector with probable-lock-detection

In this paper, we present a novel high speed binary phase detector for clock and data recovery (CDR) applications. We also introduce a new probable-lock detector which is used to alleviate the classic tradeoff between acquisition time and jitter. The probable-lock detector is used in the CDR to generate a higher gain during the acquisition process and reduce this gain when clock and data are locked. The proposed solutions have been designed in a 180 nm CMOS technology using standard cells and have been incorporated in a 1 Gb/s mixed-signal CDR. Simulation results validate the proposed solutions and confirm that the system operates as expected.