Author :
Lee, Hyun-Woo ; Kim, Yong-Hoon ; Yun, Won-Joo ; Park, Eun Young ; Lee, Kang Youl ; Kim, Jaeil ; Kim, Kwang Hyun ; Jung, Jong Ho ; Kim, Kyung Whan ; Rye, Nam Gyu ; Kim, Kwan-Weon ; Chun, Jun Hyun ; Kim, Chulwoo ; Choi, Young-Jung ; Chung, Byong-Tae ; Kih,
Abstract :
A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.
Keywords :
DRAM chips; clocks; delay lines; delay lock loops; jitter; low-power electronics; DRAM interface; DRAM process technology; OR-AND DCC; digital delay locked loop; dual-DLL architecture; duty cycle correction; duty error; external clock; frequency 1 GHz; high frequency operation; low jitter; low power operation; merged dual coarse delay line; power 7.7 mW; racing mode; size 54 nm; time 1 ns; voltage 1.35 V; Delay lines; Detectors; Energy consumption; Frequency; Jitter; Logic gates; Power engineering and energy; Random access memory; SDRAM; Shift registers;
