A high performance parallel transform and quantization architecture for H.264 decoder

Author

Hu, Xia-Rong ; Liu, Bu-Ming ; Zhang, Chi

Author_Institution

Sch. of Microelectron. & Solid State Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2009

fDate

23-25 July 2009

Firstpage

1059

Lastpage

1060

Abstract

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 decoder standard. The architecture can be developed to be used in high-resolution applications such as high definition television (HDTV) and digital cinema.

Keywords

code standards; decoding; quantisation (signal); transform coding; video coding; H.264 decoder standard; forward transform; high-performance parallel transform; inverse transform; quantization architecture; real-time implementation; Costs; Decoding; Discrete transforms; Frequency domain analysis; HDTV; Hardware; Low pass filters; Microelectronics; Quantization; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on

Conference_Location

Milpitas, CA

Print_ISBN

978-1-4244-4886-9

Electronic_ISBN

978-1-4244-4888-3

Type

conf

DOI

10.1109/ICCCAS.2009.5250349

Filename

5250349

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3385281