Application-level pipelining on Hierarchical NoC

Author

Wei, Yi ; Hongbing, Pan ; Peng, Pan ; Li, Li ; Minglun, Gao ; Ning, Hou ; Gaoming, Du ; Duoli, Zhang

Author_Institution

Inst. of VLSI Design, Nanjing Univ., Nanjing, China

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3873

Lastpage

3876

Abstract

Multiprocessor System-on-Chip is a promising solution for the high performance Embedded System. This paper is based on an independent research about Hierarchical NoC (Network-on-chip). By integrating 16 ARM cores in the FPGA board, we can bring out the four-channel fade-in and fade-out for real-time streaming media. We present two parallel models for our multiprocessor. One is fine-grained parallelization, with which the speed-up is 7.6, the other module is coarse-grained parallelization, with which the speed-up is higher than 9.2.

Keywords

network-on-chip; pipeline arithmetic; application-level pipelining; coarse-grained parallelization; fine-grained parallelization; hierarchical NoC; multiprocessor system-on-chip; network-on-chip; real-time streaming media; Computer architecture; Hardware; Multicore processing; Network-on-a-chip; Object oriented modeling; Pipeline processing; SDRAM; System performance; Very large scale integration; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537706

Filename

5537706