Energy model of CMOS gates using a piecewise linear model

We extend our previous work on delay estimation with a piecewise linear model and propose efficient formulae for power estimation including short-circuit power, dynamic power, and leakage power. Our piecewise linear model is a modified switched-resistor model considering transistor saturation current with a linearized BSIM3 capacitance model, which allows to compute energy and output slopes for static CMOS logic gates. Accuracy of the energy formulae are within 10% of SPICE in the worst case for complex static CMOS gates using CMOS 0.5um and 180nm technologies. The proposed energy formulas are computationally efficient, scalable, and suitable for fast power conscious CAD tools for large CMOS circuit simulations.