Resistive extraction of polysilicon gate linewidth

Author

Miles, Glen ; Hook, Terence ; Faucher, Margaret ; Morrett, Kent

Author_Institution

IBM Microelectron. Div., Essex Junction, VT, USA

fYear

1997

fDate

10-12 Sep 1997

Firstpage

24

Lastpage

29

Abstract

The polysilicon gate linewidth manufacturing control strategy typically includes an electrical resistance measurement to extract the gate dimension. The extraction method usually assumes that wide (reference) and narrow (gate dimension) resistors have the same absolute sheet resistance. However, upon deeper examination, we found that this assumption is frequently invalid, submicron resistors do not necessarily have the same sheet resistance as wide resistors. Moreover, N-type and P-type narrow resistors exhibit quite divergent behaviors

Keywords

electric resistance measurement; elemental semiconductors; semiconductor technology; silicon; Si; electrical resistance measurement; gate dimension extraction; manufacturing control; polysilicon gate linewidth; resistor; sheet resistance; CMOS technology; Capacitors; Electric resistance; Electrical resistance measurement; Manufacturing; Microelectronics; Oxidation; Resistors; Rivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI

Conference_Location

Cambridge, MA

ISSN

1078-8743

Print_ISBN

0-7803-4050-7

Type

conf

DOI

10.1109/ASMC.1997.630699

Filename

630699