Rapid design and prototyping of universal soft demapper

Rapid advancements in wireless communication standardization is leading toward the evolution of flexible radio platforms. At the same time, the resulting severe time-to-market constraints make inevitably resorting to new design methodologies to shorten the development cycle. In this paper we are presenting the steps involved in rapid design, validation, and prototyping of the first multi standard ASIP-based universal demapper. The presented ASIP provides flexibility to support any modulation type using up to 8 bits per symbol both in turbo and non-turbo context. The rapid development flow has been described starting from ASIP modeling in LISA ADL till the FPGA implementation. Using a logic emulation board integrating Virtex 5 LX330 FPGA, the prototype achieves a throughput of 102 Mega LLR/sec for Gray mapped 16-QAM constellation at a clock frequency of 156 MHz. The highly reduced size of the ASIP, comprising of 1596 (0.7%) slice registers, 2627 (1.2%) slice LUTs and 6 DSP48Es, enables the user to achieve even higher throughputs by using multi-ASIP architecture.