A VLSI architecture of cost calculation and all-zero block detection for fractional motion estimation

To improve the coding gain, many fractional motion estimation engines contain processing units for calculating the sum of absolute hadamard-transformed differences, which take about half of the overall area. In this paper, a new cost of the “Sum of Absolute Half-Transformed Differences” is proposed for H.264/AVC. The VLSI architecture of the new processing unit saves about 50% of the area with a very slight loss of the coding gain. Besides, an efficient all-zero block detection method could be easily implemented in this architecture, which can detect about 80% more all-zero blocks compared to the traditional approaches.