Parallel scalable hardware architecture for hard Raptor decoder

In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implementation in an embedded processor. We demonstrate the superiority of our proposed architecture in terms of performance (by a factor 12), power and energy dissipation (by a factor of 15). We also include the hardware resource requirements in the comparison. Furthermore, the proposed hardware architecture is parameterized and easily scalable. The data processing word size has been successfully extended up to 1024 bits and fitted within the chosen FPGA hardware platform.