Title :
On the comparison of ΔIDDQ and IDDQ testing
Author_Institution :
Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
Abstract :
The purpose of this paper is to compare differential Iddq to Iddq itself; in their capabilities of detecting active current defects/faults, as bridging faults. To perform this comparison, a mathematical framework is developed, based on assumptions validated with data from the Sematech experiment S121. The comparison results reveal that the probability of false test decision can be reduced by orders of magnitude by using differential Iddq instead of Iddq. Based on the same framework, we also show that a wise vector selection may contribute to decrease by orders of magnitude the probability of a false test decision. Finally, we investigate the applicability of differential Iddq with deep-submicron technologies, by estimating the number of (pairs of) vectors required to achieve a given test qualify level. The proposed framework and the results help to understand the tendencies and to identify the requirements in order to meet the challenges of deep-submicron current testing
Keywords :
VLSI; electric current measurement; integrated circuit testing; IDDQ testing; VLSI; active current defect; active current fault; bridging fault; deep-submicron IC technology; differential IDDQ testing; false test decision probability; wise vector selection; Circuit faults; Circuit testing; Current measurement; Electrical fault detection; Fault detection; Leakage current; Performance evaluation; Process design; Switching circuits; System-on-a-chip;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766658
