• DocumentCode
    338609
  • Title

    A flexible path selection procedure for path delay fault testing

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    152
  • Lastpage
    159
  • Abstract
    We describe a path selection procedure that selects target faults for path delay fault test generation. Since large numbers of path delay faults may be untestable, the proposed procedure does not select a fixed set of paths. Instead, it provides compactly represented subsets of paths, referred to as super-paths, and allows the test generation procedure to select one path out of each subset based on testability considerations
  • Keywords
    delays; digital integrated circuits; integrated circuit testing; logic testing; flexible path selection procedure; path delay fault testing; super-paths; test generation procedure; testability considerations; Circuit faults; Circuit testing; Cities and towns; Propagation delay; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1999. Proceedings. 17th IEEE
  • Conference_Location
    Dana Point, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-0146-X
  • Type

    conf

  • DOI
    10.1109/VTEST.1999.766659
  • Filename
    766659