Title :
High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels
Author :
Dong, Yiping ; Lin, Zhen ; Li, Yan ; Watanabe, Takahiro
Author_Institution :
Waseda Univ., Tokyo, Japan
fDate :
May 30 2010-June 2 2010
Abstract :
Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CP-SPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.
Keywords :
network-on-chip; neural nets; 5-port 2-virtual channels; NIRGAM NoC simulator; artificial neural network; high performance implementation; networks on chip; neural networks; Artificial neural networks; Costs; Data communication; Decoding; Network-on-a-chip; Neural networks; Neurons; Routing; Switches; Table lookup;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537747