DocumentCode :
3386131
Title :
P3A: a partitionable parallel/pipeline architecture for real-time image processing
Author :
Gray, C. Thomas ; Liu, Wentai ; Hughes, Thomas ; Cavin, Ralph ; Chen, Sh-shing
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Volume :
ii
fYear :
1990
fDate :
16-21 Jun 1990
Firstpage :
529
Abstract :
A high-performance partitionable parallel/pipeline architecture (P 3A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P3A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining
Keywords :
computerised picture processing; parallel architectures; pipeline processing; real-time systems; butterfly; computerised picture processing; concurrency; image processing; partitionable parallel/pipeline architecture; real-time; shuffle-exchange; tree algorithms; wraparound memory; Computer architecture; Computer vision; Concurrent computing; Embedded computing; Fourier transforms; Image processing; Parallel processing; Pipeline processing; Real time systems; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Pattern Recognition, 1990. Proceedings., 10th International Conference on
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-8186-2062-5
Type :
conf
DOI :
10.1109/ICPR.1990.119421
Filename :
119421
Link To Document :
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