REDO-random excitation and deterministic observation-first commercial experiment

Author

Grimaila, Michael R. ; Lee, Sooryong ; Dworak, Jennifer ; Butler, Kenneth M. ; Stewart, Bret ; Balachandran, Hari ; Houchins, Bryan ; Mathur, Vineet ; Park, Jaehong ; Wang, Li C. ; Mercer, M. Ray

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1999

fDate

1999

Firstpage

268

Lastpage

274

Abstract

For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75 K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today´s state of the art tools and techniques

Keywords

VLSI; automatic test pattern generation; fault diagnosis; integrated circuit testing; logic testing; IC testing; REDO; defective part level; deterministic observation; logic gates; nontarget defect detection; random excitation; stuck-at faults; test pattern generation techniques; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Fault detection; Logic gates; Logic testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1999. Proceedings. 17th IEEE

Conference_Location

Dana Point, CA

ISSN

1093-0167

Print_ISBN

0-7695-0146-X

Type

conf

DOI

10.1109/VTEST.1999.766675

Filename

766675