Title :
Defect-oriented test scheduling
Author :
Jiang, Wanli ; Vinnakota, Bapiraju
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
Test time can be reduced by ordering tests so as to fail defective units early in the test process. An ordering algorithm requires information on the ability of tests to detect defective units. We obtain it by applying all possible tests to a small subset of manufactured units and assume the information obtained from this sub-set is representative. We develop a simple polynomial-time heuristic which uses the information from the sample set to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. Optimal test ordering algorithms require execution time which is exponential in the number of tests applied. In our experiments, the heuristic results in a significant reduction in test time for manufactured digital and analog ICs
Keywords :
VLSI; analogue integrated circuits; automatic testing; circuit analysis computing; digital integrated circuits; integrated circuit testing; scheduling; analog IC; defect-oriented test scheduling; digital IC; globally optimal solutions; manufactured ICs; polynomial-time heuristic; test ordering algorithm; test time reduction; Costs; Ear; Heuristic algorithms; Integrated circuit testing; Job shop scheduling; Manufacturing; Processor scheduling; Product design; Read only memory; Scheduling algorithm;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766700
