DocumentCode :
3386257
Title :
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm
Author :
Youness, Hassan ; Wahdan, Abdel-Moniem ; Hassan, Mohammed ; Salem, Ashraf ; Moness, Mohammed ; Sakanushi, Keishi ; Takeuchi, Yoshinori ; Imai, Masaharu
Author_Institution :
Minia Univ., Egypt
fYear :
2010
fDate :
May 30 2010-June 2 2010
Firstpage :
3729
Lastpage :
3732
Abstract :
In this paper, efficient hardware-software (HW-SW) partitioning technique based on high performance scheduling and mapping algorithms on multiple cores is presented. The scheduling and mapping algorithms produce the optimality of mapping tasks onto cores. The partitioning technique reduces the overall execution time and number of buses among the cores. The viability and potential of the proposed algorithms are demonstrated by extensive experimental results to conclude that the proposed algorithms are efficient scheme to obtain the optimality of scheduling, mapping and partitioning with hard and large task graph problems.
Keywords :
hardware-software codesign; logic design; microprocessor chips; multiprocessing systems; HW-SW partitioning technique; hardware-software partitioning; high performance scheduling; mapping algorithm; multiple cores; optimal scheduling; Computational efficiency; Costs; Field programmable gate arrays; Graphics; Hardware; Optimal scheduling; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
Type :
conf
DOI :
10.1109/ISCAS.2010.5537755
Filename :
5537755
Link To Document :
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