Title :
Distinguishable error detection method for Network on Chip
Author :
Jiang, Chung-Huang ; Tsai, Kun-Lin ; Lai, Feipei ; Tsai, Shun-Hung
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
In modern Network-on-Chip (NoC) design, how to guarantee the data correctness from source IP to destination IP becomes an important issue. Error detection can be one of the solutions of this problem. In this paper, a distinguishable error detection method and the corresponding router are proposed to solve the data correctness problem. In the proposed method, the significant or critical data will be checked strictly while the other data will be checked slightly. Simulation results demonstrate that the proposed method not only provides an effective error detection scheme but also has better power-delay product than conventional technique.
Keywords :
error detection; industrial property; network-on-chip; data correctness problem; destination IP; distinguishable error detection method; effective error detection scheme; network on chip; source IP; Computer errors; Costs; Crosstalk; Data communication; Error correction; Integrated circuit interconnections; Network-on-a-chip; Switches; Transistors; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537756
