DocumentCode :
3386344
Title :
Guaranteeing spike arrival time in multiboard & multichip spiking neural networks
Author :
Belhadj, Bilel ; Tomas, Jean ; Malot, Olivia ; Bornat, Yannick ; Kaoua, Gilles N. ; Renaud, Sylvie
Author_Institution :
Dept. of Microelectron., Bordeaux Univ., Bordeaux, France
fYear :
2010
fDate :
May 30 2010-June 2 2010
Firstpage :
377
Lastpage :
380
Abstract :
Large-scale spiking neural networks (SNN) are generally run on distributed and parallel architectures with multiple computation nodes. These architectures induce extra delays due to the node-to-node communication process. In multiboard & multichip SNNs, important delays may affect spike arrival time and, thus, can alter simulation results. In this work, we propose a method aiming to guarantee spike arrival time with arbitrary prefixed deadlines. The communication architecture is based on the token-passing access policy to grant access to shared communication channels. We show that several network parameters must be set carefully if spikes have to meet their deadlines. Parameters are chosen by taking into account the communication channel bandwidth, the arbitrary deadlines and the worst case situation that can happen in generating neural activity in SNNs. As proof of concept, we have built a system that emulates up to 120 analog Hodgkin-Huxley neurons spread across 6 boards. Experimental results show that whatever it happens (unless there is a network fault), spikes reach their destination with a maximum delay of 5 microseconds.
Keywords :
neural chips; neural net architecture; parallel architectures; telecommunication channels; SNN; analog Hodgkin-Huxley neurons; arbitrary prefixed deadlines; communication architecture; communication channel bandwidth; distributed architecture; large-scale spiking neural networks; multiboard spiking neural networks; multichip spiking neural networks; network parameters; neural activity; node-to-node communication process; parallel architectures; shared communication channels; spike arrival time; token-passing access policy; Communication channels; Computational modeling; Computer architecture; Computer networks; Concurrent computing; Delay effects; Distributed computing; Large-scale systems; Neural networks; Parallel architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
Type :
conf
DOI :
10.1109/ISCAS.2010.5537758
Filename :
5537758
Link To Document :
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