• DocumentCode
    3386513
  • Title

    OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic

  • Author

    Fuhrer, R.M.

  • Author_Institution
    Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
  • fYear
    1999
  • fDate
    7-11 Nov. 1999
  • Firstpage
    7
  • Lastpage
    13
  • Abstract
    The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. The OPTIMIST (OPTImal MInimization of STates) algorithm (R.M. Fuhrer et al., 1997) was the first general solution to this problem for synchronous finite state machines (FSMs). In this paper, we present the first solution for asynchronous FSMs. This paper makes two contributions. First, we introduce OPTIMISTA (OPTIMIST-Asynchronous), a new algorithm which guarantees optimum 2-level output logic for asynchronous FSMs. In asynchronous machines, output logic is often critical: it usually determines the machine latency. The algorithm is formulated as a binate constraint satisfaction problem, which is solved using a binate solver. The second contribution is a novel alternative result: the unreduced machine itself can be used directly to obtain minimum-cardinality output logic. Thus, this paper presents two approaches: using OPTIMISTA, which simultaneously performs state and logic minimization; or using no state reduction (if output logic cardinality is of sole interest). Extensions for literal optimization, targetted to multi-level logic, are also proposed.
  • Keywords
    asynchronous circuits; asynchronous sequential logic; finite state machines; logic design; minimisation; OPTIMIST algorithm; OPTIMISTA algorithm; asynchronous finite state machines; binate constraint satisfaction problem; binate solver; literal optimization; logic implementation; logic minimization; machine latency; minimum-cardinality output logic; multi-level logic; optimal state minimization; optimum 2-level output logic; output logic cardinality; reduced state machine; state encodings; state reduction; state reductions; unreduced machine; Clocks; Computer science; Costs; Delay; Encoding; Logic; Minimization methods; Optimization methods; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-5832-5
  • Type

    conf

  • DOI
    10.1109/ICCAD.1999.810610
  • Filename
    810610