Title :
Concurrent logic restructuring and placement for timing closure
Author :
Jinan Lou ; Wei Chen ; Pedram, M.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
An algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each super-cell. The best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm.
Keywords :
circuit CAD; geometric programming; logic CAD; software performance evaluation; timing; MCNC benchmarks; critical paths; generalized geometric programming problem; iterative process; logic restructuring; noninferior re-mapping solutions; placement; super-cells; timing closure; Capacitance; Circuit synthesis; Clocks; Constraint optimization; Delay; Electronic design automation and methodology; Functional programming; Logic programming; Timing; Wire;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810615
