Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach

In this work we present how variance reduction techniques can be applied to Monte Carlo simulations on an FPGA platform. Variance reduction techniques improve the accuracy of Monte Carlo simulations without increasing the number of individual simulations required, and consequently, the time and resources needed. Two techniques, Stratified Sampling and Latin Hypercube, have been implemented with a parameterizable architecture that additionally allows different configurations. To verify the proposed approach we have integrated these techniques on an FPGA Gaussian Random Number Generator, obtaining a complete a hardware accelerator for Monte Carlo simulations.