Improved extrinsic information scheduling for non-binary cycle codes

Low-density parity-check codes with variable node degree two over high order Galois fields are called non-binary cycle codes. In this paper, several improved extrinsic information scheduling strategies with reduced iteration times are proposed for non-binary cycle codes. Exploiting the property of underlying sparse graphs for cycle codes, iteration times and hardware complexity including computation units and inner memories can obtain a proper trade-off using the proposed fully serial or turbo scheduling in each iteration. In this way, significant error correction performance can be obtained with less hardware resources and iterations.