Implementation of large-integer hardware multiplier in Xilinx FPGA

Implementation of wide multipliers for high performance is usually performed by the vendor synthesis/place and route software tool. This paper presents a partition algorithm for large integer multipliers with speed as optimization criteria. The generated solution uses built-in high-speed arithmetic blocks available in the current generation of Xilinx FPGA chip. The proposed technique has shown reduction in delay of more than 30% when compared to both Xilinx Coregen and Xilinx Synthesis Tools generated models.