Fast and reliable WLR monitoring methodology for assessing thick dielectrics test structures integrated in the kerf of product wafers

In this work the optimisation of an in-line stress for thick dielectric layers, SMU set up, tester equipment and layout of test structures for fast WLR Monitoring is described. It is shown that a current ramp is the optimum solution to avoid any influence on adjacent chips from the stress, large melted areas of the test structures and/or the melting of the interconnect to the structure. The work focuses on Metal-Insulator-Metal capacitors, but similar observations can be also obtained from thick MOS gate oxides.