DocumentCode :
3386851
Title :
Modeling and testing comparison faults for ternary content addressable memories
Author :
Li, Jin-Fu ; Lin, Chou-Kun
Author_Institution :
Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan
fYear :
2005
fDate :
1-5 May 2005
Firstpage :
60
Lastpage :
65
Abstract :
This paper presents the comparison faults of TCAMs based on physical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Accordingly, several comparison fault models are proposed. A March-like test algorithm for comparison faults is also proposed. The test algorithm only requires 4N Write operations, 3N Erase operations, and (4N+2B) Compare operations to cover 100% comparison faults for an N × B-bit TCAM. Compared with the previous work, the proposed test algorithm has lower time complexity for TCAMs with wide words and the time complexity is independent of the number of stuck-on faults. Also, the algorithm can cover all defects that cause a failed Compare operation. Moreover, it can be realized by built-in self-test circuitry with lower area cost.
Keywords :
built-in self test; computational complexity; content-addressable storage; fault diagnosis; integrated circuit testing; integrated memory circuits; March-like test algorithm; TCAM; built-in self-test circuitry; circuit nodes; compare operations; comparison faults; erase operations; fault models; physical defects; stuck-on faults; ternary content addressable memories; time complexity; transistor stuck-open faults; write operations; Associative memory; Bandwidth; Cams; Circuit faults; Circuit testing; Decoding; Encoding; Random access memory; Registers; Signal generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2314-5
Type :
conf
DOI :
10.1109/VTS.2005.57
Filename :
1443400
Link To Document :
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