Title :
An integrated algorithm for combined placement and libraryless technology mapping
Author :
Yanbin Jiang ; Sapatnekar, S.S.
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
Abstract :
This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state-space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits.
Keywords :
circuit layout CAD; heuristic programming; integrated software; search problems; software performance evaluation; state-space methods; technology CAD (electronics); CPU times; benchmark circuits; heuristics; integrated algorithm; libraryless technology mapping; placement; search speed; state-space search mechanism; Algorithm design and analysis; Capacitance; Central Processing Unit; Delay; Integrated circuit interconnections; Libraries; Logic; Space technology; State-space methods; Wire;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810630
