DocumentCode
3387026
Title
Synthesis of X-tolerant convolutional compactors
Author
Rajski, Janusz ; Tyszer, Jerzy
Author_Institution
Mentor Graphics Corp., Wilsonville, OR, USA
fYear
2005
fDate
1-5 May 2005
Firstpage
114
Lastpage
119
Abstract
The paper presents a very efficient method for synthesis of convolutional compactors capable of tolerating a number of unknown states in a single time frame while providing very high compaction ratios.
Keywords
built-in self test; data compression; fault tolerance; integrated circuit testing; X-tolerant convolutional compactor synthesis; embedded testing; fault tolerance; Circuit testing; Combinational circuits; Compaction; Convolutional codes; Graphics; Impulse testing; Manufacturing; Paper technology; Polynomials; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
ISSN
1093-0167
Print_ISBN
0-7695-2314-5
Type
conf
DOI
10.1109/VTS.2005.81
Filename
1443408
Link To Document