Techniques for improving the efficiency of sequential circuit test generation

Author

Xijiang Lin ; Pomeranz, I. ; Reddy, S.M.

Author_Institution

Mentor Graphics Corp., Wilsonville, OR, USA

fYear

1999

fDate

7-11 Nov. 1999

Firstpage

147

Lastpage

151

Abstract

New techniques are presented in this paper to improve the efficiency of a test generation procedure for synchronous sequential circuits. These techniques aid the test generation procedure by reducing the search space, carrying out non-chronological backtracking, and reusing the test generation effort. They have been integrated into an existing sequential test generation system MIX to constitute a new system, named MIX-PLUS. The experimental results for the ISCAS-89 and ADDENDUM-93 benchmark circuits demonstrate the effectiveness of these techniques in improving the fault coverage and test generation efficiency.

Keywords

automatic test pattern generation; backtracking; logic testing; sequential circuits; ADDENDUM-93 benchmark circuits; ISCAS-89 benchmark circuits; MIX; MIX-PLUS; fault coverage; nonchronological backtracking; search space reduction; sequential circuit test generation efficiency; synchronous sequential circuits; Benchmark testing; Circuit faults; Circuit testing; Computer graphics; Genetics; Logic testing; Observability; Sequential analysis; Sequential circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

ISSN

1092-3152

Print_ISBN

0-7803-5832-5

Type

conf

DOI

10.1109/ICCAD.1999.810639

Filename

810639