DocumentCode
3387093
Title
SoC design challenges in the deep-sub micron era
Author
Paliwal, Neeraj
Author_Institution
NXP Semiconductors, The Netherlands
fYear
2008
fDate
Aug. 31 2008-Sept. 3 2008
Firstpage
7
Lastpage
8
Abstract
This plenary session looks at the challenges facing the SoC design world today. We will discuss two new trends and innovation areas: 1. Technology, 2. Design Methodology
Keywords
Costs; Design methodology; Electronic design automation and methodology; FinFETs; High K dielectric materials; High-K gate dielectrics; Investments; Lithography; Technological innovation; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location
St. Julien´s
Print_ISBN
978-1-4244-2181-7
Type
conf
DOI
10.1109/ICECS.2008.4675123
Filename
4675123
Link To Document