Sub-quarter micron SRAM cells stability in low-voltage operation: a comparative analysis

Author

Semenov, Oleg ; Pavlov, Andrei ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

2002

fDate

21-24 Oct. 2002

Firstpage

168

Lastpage

171

Abstract

Comparative analysis of the conventional 6T and recently proposed loadless 4T CMOS SRAM cells is performed. Based on HSPICE simulations for 0.18-μm technology, we compared the stability of the aforementioned cells to temperature and process (V_TH, L_eff, T_OX) variations as well as the cells robustness in low-voltage operation. We found that at V_DD = 1.2 V the loadless 4T cell has a 20% higher static noise margin (SNM) and 1.5 times lower sensitivity to the V_TH fluctuations than the 6T cell. On the other hand, the 4T cell has a stronger read current degradation at reduced V_DD. The analytical model for SNM calculation of the loadless 4T CMOS SRAM cell has been developed.

Keywords

CMOS memory circuits; SPICE; SRAM chips; circuit stability; integrated circuit modelling; integrated circuit noise; low-power electronics; 0.18 micron; 6T cell; CMOS SRAM stability; HSPICE simulation; analytical model; loadless 4T cell; low-voltage operation; process fluctuations; read current; static noise margin; temperature fluctuations; Analytical models; CMOS technology; Degradation; Fluctuations; Noise robustness; Performance analysis; Random access memory; Robust stability; Stability analysis; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2002. IEEE International

Print_ISBN

0-7803-7558-0

Type

conf

DOI

10.1109/IRWS.2002.1194260

Filename

1194260