Effective TARO pattern generation

Author

Park, Intaik ; Al-Yamani, Ahmad ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

2005

fDate

1-5 May 2005

Firstpage

161

Lastpage

166

Abstract

TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to identify any ATPG tool that can generate TARO test patterns directly. This paper describes a technique to use an existing transition fault ATPG tool to efficiently generate TARO test patterns. This technique was used to generate TARO patterns for the ELF35 test chip. When these patterns were applied to the ELF35 chips, all of the defective chips were discovered (no test escapes).

Keywords

automatic test pattern generation; fault location; integrated circuit testing; ATPG tool; ELF35 test chip; TARO test pattern generation; defective chip discovery; fault location; transition fault test patterns; Automatic test pattern generation; Fault detection; Fault location; Flip-flops; Geophysical measurement techniques; Ground penetrating radar; Large scale integration; Logic testing; Test pattern generators; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2005. Proceedings. 23rd IEEE

ISSN

1093-0167

Print_ISBN

0-7695-2314-5

Type

conf

DOI

10.1109/VTS.2005.43

Filename

1443415

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3387163